Output buffer circuits (also called "off-chip driver circuits") are generally provided in integrated circuit chips, wherein they constitute interface circuits for driving external load impedances which are represented by other integrated circuit inputs and by parasitic components introduced by the printed circuit board (PCB) interconnection lines.
As far as switching speed is concerned, a primary role is played by the capacitive component of an output buffer circuit load impedance. It follows that one of the main requirements of an output buffer circuit is its capability of supplying and sinking high currents.
In modem VLSI chips fabricated with sub-micron CMOS technologies, signal transition times of a few hundreds of picoseconds are common. It has therefore been possible to design output buffer circuits, substantially consisting of CMOS inverters, which can deliver current at as high a rate as 50 mA/ns.
Since, however, the internal (on-chip) power supply and ground lines which supply buffer circuits are respectively connected to the external power supply and ground voltage rails on the PCB through the chip package pins, which introduce series parasitic inductances ranging from 5 nH to 15 nH, considerable power supply voltage drops or ground voltage peaks (named "inductive switching noise voltage") are produced when such a fast current variation takes place, in accordance to the inductor equation V=LdI/dt. Once the cited values for L and dI/dt have been introduced into the equation, noise voltage values in the range of 500 mV are obtained. The noise voltage appears as an undesired undershoot or overshoot in the internal power supply or ground voltage levels with respect to the PCB power supply or ground voltage rails, respectively, when the output buffer supplies current to or sinks current from the load.
The noise voltage thus generated is harmful under many respects. First of all, non-switching or "quiet" off-chip driver circuits which are supplied by the same internal power supply and ground lines which supply the switching off-chip driver circuit transmit the power supply and ground voltage bounces to their outputs, through low-impedance paths represented by transistors operated in the linear region; if said voltage bounces exceed a threshold level, they induce spurious transitions at the inputs of other integrated circuits. Secondly, input buffer circuits supplied by the same internal power supply and ground lines which supply the switching off-chip drivers transmit, for the same reason, the power supply and ground voltage bounces to the chip core, whose circuits are commonly supplied by separated internal power supply and ground lines, inducing spurious transitions. Thirdly, switching speed is degraded, since the voltage bounces shrink the gap between the power supply and ground voltage levels.
The inductive switching noise problem is exacerbated when more than one off-chip driver circuit switches at the same time, a circumstance which is more and more frequent in view of the increase in operating frequencies and integration of functions in the same chip. It has been recognized that four to eight simultaneously switching off-chip driver circuits, each with medium current handling capability, are sufficient to corrupt the data at the output of quiet driver circuits which are supplied by the same internal power supply and ground lines.
Switching noise is also exacerbated by reflections and ringings occurring at the output of quiet off-chip driver circuits caused by the PCB trace parasitic components. A possible solution is to provide large capacitive loads on the PCB traces to damp the voltage bounces transmitted by quiet off-chip driver circuits. While however the output loading condition can be effective in damping or magnifying noise voltage bounces at the output of quiet off-chip driver circuits, this is not the case for the switching off-chip driver circuits, since it has been recognized that peak values in the power supply voltage undershoot or ground voltage overshoot take place when the transistors constituting the switching off-chip driver circuits are still operated in the saturation region and the driver load is therefore decoupled from the internal power supply and ground lines by a relatively large impedance. Experiments have shown that the peak value of the current supplied or sinked by a driver circuit has little influence on the value of voltage bounces due to the nature of inductive noise, the most important parameter being represented by the current time derivative (current slew rate).
An obvious way to mitigate the inductive switching noise problem consists in reducing the parasitic inductances inherent to the package pins. In the practice this is achieved by providing two or more pads for the internal power supply and ground lines, which are then parallel bonded to the external power supply and ground rails. In this case, 20% to 30% of the total number of chip pads are generally dedicated to the internal power supply and ground lines. Also, special packages can be used that introduce minimum stray inductances. In both cases, high production costs are incurred.
Another way to minimize the switching noise problem aims at controlling the time derivative of the current supplied or sinked by the output buffer circuits. This can be achieved by providing control circuits that control the switching of output buffers in such a way that they supply or sink current in a controlled and specified manner under all operating conditions. Such control circuits are known as "current slew rate control circuits."
A first known solution provides for splitting each output buffer circuit in a plurality of parallel stages. The output buffer is controlled by a control circuit which achieves current slew rate control by preventing short-circuit currents ("crowbar currents") during each output buffer stage switching, and by turning on different output buffer stages in successive steps. A series connection of logic gates is used to introduce delays between the signals controlling the different off-chip driver stages.
Such a circuit allows poor current slew rate tracking over temperature, process and supply voltage variations. The control of the current slew rate dramatically deteriorates when the integrated circuit is operated in the so-called fast conditions (low temperature, high supply voltage), since the output buffer current capability increases and the logic gate propagation delay decreases. When, on the other hand, the integrated circuit is operated in slow conditions (high temperature, low supply voltage), the increase in the logic gate propagation delay causes an unacceptable increase in the switching times of the output buffers. Furthermore, the control circuit shows a dependence on the external load of the output buffer circuit: the larger the capacitive component of the external load and the longer the PCB traces, the more the output buffer stages get turned on before the output voltage completes its transition, and the higher is the current slew rate control degradation. Also, each output buffer stage is abruptly turned on, since the respective control signal, being fully amplified by the serially connected logic gates, shows low transition times; this causes the output buffer to supply or sink an irregular current, with high slew rate which induces internal power supply and ground bounces. Finally, such a control circuit has poor flexibility, being tailored for particular output buffers, and uses considerable chip area.
In a second known solution the output buffer circuits are again split in a plurality of stages, connected in parallel between the internal power supply and ground lines and with common output. Current slew rate control is achieved by exploiting the inherent RC delays in the control electrodes of the output buffer stages: the gate electrode of the P-channel and N-channel MOSFETs constituting each stage is laid out as a serpentine through the stages, so that they are turned on with delays defined by the parasitic resistance and capacitance associated with the control electrode material. Such solution shows limitations similar to those previously described.
Other solutions use feedback paths to control the switching of successive output buffer stages on the basis of the voltage levels of the output buffer output signal, instead of controlling the switching according to internally generated delays.
The presence of feedback significantly complicates the design of the physical layout of the output buffer circuits. Furthermore, if positive feedback is adopted, temperature, voltage supply and process variation tracking is compromised, while the use of negative feedback requires the off-chip loading conditions of the output buffers to be known. Such solutions therefore do not lend themselves to the design of general purpose current slew rate control circuits.
Finally, in the memory chip design field, output buffer current slew rate control circuits are known that rely on peculiar memory operating conditions. Such circuits reduce the current time derivative by precharging the output buffer load impedance to an intermediate voltage level between the power supply and ground voltage levels before the output buffer is made to switch. These circuits, however, are only exploitable if special assumptions regarding the output bus protocol can be made, and are therefore unsuitable for general purpose output buffer circuits.